Keynote Speakers
Walden C. Rhines
Silvaco Group Inc., USA
Title: Breaking Computer Design Traditions
Abstract: Building upon a history of managing chip development programs, Dr. Rhines will trace the evolution from traditional Von Neumann architectures to new approaches to capturing the benefits of parallelism. Using an example of a chip design that he recently completed, he will describe the likely evolution of quantum-proof cybersecurity using fully homomorphic encryption.
Biography: WALDEN C. (Wally) RHINES is CEO of Silvaco Group, Inc.,(NASDAQ: SVCO), a company providing software for electronic design automation. The previous five years, he was President and CEO of Cornami, Inc., a fabless semiconductor and software company focused upon fully homomorphic encryption. For 25 years, he was CEO of Mentor Graphics (NASDAQ: MENT) and Chairman of the Board for 17 years. During his tenure at Mentor, revenue nearly quadrupled and market value of the company increased 10X. Prior to joining Mentor Graphics, Dr. Rhines was Executive Vice President, Semiconductor Group, responsible for Texas Instrument's worldwide semiconductor business. Dr. Rhines is Chairman of the Board of QORVO and Caspia, and has served on the boards of Cirrus Logic, TriQuint Semiconductor, Global Logic, PTK Corp., Silvaco and Pallidus and as Chairman of the Electronic Design Automation Consortium (five two-year terms). He is a Lifetime Fellow of the IEEE and a member of the National Academy of Engineering. Dr. Rhines holds a Bachelor of Science degree in engineering from the University of Michigan, a Master of Science and PhD in materials science and engineering from Stanford University, an MBA from Southern Methodist University and Honorary Doctor of Technology degrees from the University of Florida and Nottingham Trent University. In 2021, the Global Semiconductor Alliance honored Dr. Rhines, with its prestigious Dr. Morris Chang Exemplary Leadership Award.
Hai "Helen" Li
Duke University, USA
Title: Big AI, Tiny Devices: Bridging the Gap Between Models and Edge Systems
Abstract: As artificial intelligence (AI) continues to transform industries, state-of-the-art models have grown dramatically in size and capability. Yet deploying these models on resource-constrained edge devices remains a fundamental challenge. Smartphones, wearables, and IoT systems operate under strict limits in compute, memory, power, and communication, creating a widening gap between the demands of modern AI and the realities of edge hardware. This talk explores how to bridge this gap and bring powerful AI to small devices. We begin by examining how hardware characteristics shape the design of efficient deep neural networks, highlighting techniques such as quantization and pruning. We then discuss system-level approaches to reduce the cost of both inference and training in distributed and collaborative edge AI settings. Finally, we present evolving design philosophies for building edge AI systems that are not only efficient but also scalable, robust, and secure.
Biography: Hai (Helen) Li is the Marie Foote Reel E'46 Distinguished Professor and Department Chair of the Electrical and Computer Engineering Department at Duke University. She received her B.S. and M.S. degrees from Tsinghua University and her Ph.D. degree from Purdue University. Her research interests include neuromorphic circuits and systems for brain-inspired computing, machine learning acceleration and trustworthy AI, conventional and emerging memory design and architecture, and software and hardware co-design. Dr. Li served/serves as the Associate Editor-in-Chief and Associate Editor for multiple IEEE and ACM journals. She was the General Chair or Technical Program Chair of multiple IEEE/ACM conferences and the Technical Program Committee member of over 30 international conference series. Dr. Li has received many awards, including the IEEE Edward J. McCluskey Technical Achievement Award, Ten-Year Retrospective Influential Paper Award from ICCAD, TUM-IAS Hans Fischer Fellowship from Germany, ELATE Fellowship, nine best paper awards, and another ten best paper nominations from IEEE/ACM. Dr. Li is a fellow of AAAS, ACM, IEEE, and NAI.
Travis S Humble
Oak Ridge National Laboratory, USA
Title: Unleashing Quantum Acceleration: Architectures to Applications
Abstract: Quantum computing offers many tantalizing opportunities for computational acceleration including superpolynomial speedups, attowatts per instruction, and impermeable protection. But how does unleashing this potential change the landscape of computing systems and their applications? Here, we examine the developing trends in quantum computing and their convergence with on-going advances in computational engineering for high-performance computing. We focus on the quantum-centric infrastructure, tools, and metrics needed for the pending shift in HPC architecture, and we conclude with the expanding range of applications to be impacted by this acceleration.
Biography: Travis Humble is director of the US Department of Energy's Quantum Science Center and a Distinguished Scientist at Oak Ridge National Laboratory. Travis leads the development of new quantum technologies and infrastructure to impact the DOE mission of scientific discovery. Travis also holds a joint faculty appointment with the University of Tennessee Bredesen Center for Interdisciplinary Research and Graduate Education to work with students in developing energy-efficient computing solutions. Travis received a doctorate in theoretical chemistry from the University of Oregon.
Vijaykrishnan Narayanan
Pennsylvania State University, USA
Title: A holistic approach to processing in memory: From device to system
Abstract: There has been a dramatic increase in data-centric workloads such as machine learning, medical analytics and personalized medicine. This talk will highlight processing in memory and fabric attached memories that enhance the efficiency of these critical memory-centric workloads. This talk will highlight efforts to incorporate computing in or near the SRAM caches, DRAM memories, and, especially advances in Ferroelectric non-volatile memory architectures. The talk will focus on the interaction across the different layers of the design stack.
Biography: Vijaykrishnan Narayanan is an Evan Pugh University Professor and Robert A Noll Chair Professor of Computer Science and Engineering and Electrical Engineering at The Pennsylvania State University. His research interests are Computer Architecture, Design Automation and Design with Emerging Technologies. He is a Fellow of IEEE, ACM, AAAS and National Academy of Inventors.
Jürgen Becker
Karlsruhe Institute of Technology, Germany
Title: Integration of Reliable HPC & AI-Accelerators
Abstract: Increasing emerging fields towards reliable networked accelerator and processor integration, incl. High Performance Computing (HPC) systems, are 'driving forces' for future silicon technologies. This results in heterogenous multi-core (MC), various vector accelerator incl. artificial intelligence (AI) and networked Edge-AI Systems integration. Here, the exploitation of parallelism and neural network partitioning by leveraging dynamic dataflow architectures to guarantee real-time requirements is essential. Multipurpose adaptivity, connectivity and reliability are crucial, especially in scaling down silicon technologies according to 'Extending Moore'. The talk will address scalable, reliable & embedded accelerator & processor IP integration, incl. open source & global ecosystem discussions in the presence of RISC-V, european chipact, selected 6G, automotive, AI, unconventional computing as well as chiplet initiatives.
Biography: Jürgen Becker is full professor for embedded electronic systems since 2001 being Head of the Institute for Information Processing Technologies (ITIV) at the Karlsruhe Institute of Technology (KIT) and served as Vice President for Education (2005-2012). His research interests are hardware/software codesign, reconfigurable computing, multicore & accelerator architectures incl. deployment, with application in automotive, industrial, medicine, robotics, avionics etc. He is director at the Computer Science Research Center (FZI) and has been coordinator of several national & european projects.
Ronald F. DeMara
University of Central Florida, USA
Title: Pathways to Leverage Emerging Devices and AI to Advance Reconfigurable Logic Device Design and Synthesis
Abstract: Pathways to future generation reconfigurable fabrics can benefit from integration of emerging devices and AI accelerated logic synthesis. In this talk, Heterogeneous Technology Configurable Fabrics (HTCFs) are introduced as versatile and advantageous hybrid post-CMOS platforms for next-generation reconfigurable computing. HTCFs assimilate the complementary roles of emerging and CMOS devices within an integrated reconfigurable array to impart field-programmable accessibility supporting both synthesis-time and run-time co-design among device technologies. Heterogeneous fabrics are comprised by a triad of emerging device blocks, CMOS logic blocks, and signal conversion blocks. Emerging device blocks utilize the strengths of non-volatile devices for non-charged based resistive/nanomagnetic storage to realize Look-Up Tables (LUTs), Configurable Logic Block (CLBs), and switching blocks. CMOS logic blocks, or other logic-optimized switching device technologies, realize functional elements such as adders and multipliers to facilitate complex functions. Their implications to enable fresh computing paradigms, facilitate new CAD tools for emerging devices, and realize low energy IoT platforms will be discussed. In summary, the opportunity for HTCFs to enable a new orthogonal dimension in reconfigurable and evolvable hardware will be emphasized. Regarding reconfigurable fabric High-Level Synthesis (HLS) optimization of the search space expands exponentially, rendering exhaustive exploration impractical. To address this bottleneck, a Genetic Evolution for Neural Optimization of Multi-objective Engineering (GENOME) workflow is feasible, which leverages Large Language Models (LLMs) to facilitate intelligent exploration of speed-accuracy trade-offs within constrained computational budgets. We demonstrate that GENOME seamlessly integrates as a surrogate evaluator within existing frameworks and achieves 44% acceleration over a baseline NSGA-II search. Furthermore, we optimize LLM performance by implementing a novel prompting strategy that co-evolves LLM context with the search population. Thus, AI assisted synthesis achieves 100% MachSuite benchmark coverage, significantly surpassing the 58% coverage of the current state of the art.
Biography: Ronald F. DeMara is a Pegasus-entitled University-level Professor in the ECE Department at the University of Central Florida, where he has been a full-time faculty member since 1993. He has completed over 350 articles, 50 funded projects as PI or Co-PI, and 58 graduates as Ph.D. dissertation and/or M.S. thesis advisor on topics of computer architecture with emphasis on emerging devices for machine learning, adaptive and reconfigurable hardware, and the digitization of STEM education. He has served ten terms as a Topical Editor or Associate Editor of various IEEE Transactions and technical conferences including General Co-Chair of GLSVLSI-2023. He has been a Keynote Speaker at IEEE iSES, IEEE IEMtronics, IEEE RAW, IEEE DCAS, and IEEE ReConFig conferences. He is a Fellow of IEEE, AAAS, and AAIA. He has received the Joseph M. Biedenbach Outstanding Engineering Educator Award from IEEE.
Patrick Schaumont
Worcester Polytechnic Institute, USA
Title: Root-cause analysis of side-channel leakage in system-on-chip design
Abstract: Side-channel leakage is a well-known vulnerability of systems processing sensitive information, and there is a myriad offensive techniques to capture, process and analyze that leakage and turn it into an effective attack. In this talk, I look at the problem of side-channel leakage from the viewpoint of the designer who faces the integration of the latest cryptographic standards and neural networks into a system-on-chip. This designer needs to test the side-channel security of the new design before tape-out, to test side-channel countermeasures and to verify integration effects. In particular, the designer is interested in identifying the root cause of a design mistake. In contrast to functional bugs, side-channel bugs are tricky to analyze and resolve, and the root-cause analysis problem in side-channel leakage is multi-layered, from firmware down to gate-level hardware. I will present several techniques that we developed in the context of concrete system-on-chip designs, and summarize the open problems in this field.
Biography: Patrick Schaumont is a Dean's Excellence Professor and Joseph Samuel Satin Distinguished Fellow in Electrical and Computer Engineering at Worcester Polytechnic Institute. His research focuses on secure, efficient, and real-time embedded computing systems. Schaumont has co-chaired leading conferences in cryptographic and secure engineering, including CHES, HOST, ASHES, and FDTC. He serves as the Editor-in-Chief for IEEE Transactions on Emerging Topics in Computing (2026-2027). He is a Fellow of the IEEE.
Sandeep Shukla
IIIT Hyderabad, India
Title: The Post Quantum Migration from the Corporate Trenches.
Abstract: The transition to Post-Quantum Cryptography (PQC) is a critical security imperative as Cryptographically Relevant Quantum Computers (CRQC) approach reality, potentially by the 2030s. This talk outlines a strategic migration framework starting with comprehensive crypto inventories and risk assessments, such as Mosca's Theorem, which evaluates the "Harvest Now, Decrypt Later" threat. Key migration challenges include the decade-long transition period for Public Key Infrastructure (PKI), the obsolescence of existing certificates, and the necessity of achieving "crypto-agility" to support evolving NIST standards like Kyber and Dilithium.
Recent research has drastically lowered the resource estimates for breaking current standards. While earlier estimates suggested 20 million noisy qubits for RSA-2048, 2025-2026 breakthroughs by researchers at Google and INRIA have reduced this to under 1 million physical qubits, or approximately 1,399 logical qubits. Crucially, Elliptic Curve Cryptography (ECC-256) is now considered a more vulnerable target, requiring only 1,193 logical qubits to break-roughly 42% fewer than the RSA equivalent. These findings underscore the urgency for organizations to adopt hybrid PQC schemes and update root CA lifespans to mitigate the impending quantum risk
Biography: Prof. Sandeep Shukla is currently a Professor and Director of IIIT Hyderabad. Before joining IIIT Hyderabad, he was Rajiv and Ritu Batra Chair Professor of Cyber Security at IIT Kanpur. He headed the department of Computer Science and Engineering at IIT Kanpur between 2017 and 2020 and served as the Poonam & Prabhu Goel Chair Professor from 2016 to 2019. He also acted as a joint coordinator of the National Interdisciplinary Centre for Cyber Security & Cyber Defense of Critical Infrastructures (C3i Center) at IIT Kanpur which he also founded and as a joint coordinator of the National Blockchain Project funded by the National Security Council Secretariat. He served as a project director of the C3i Hub a Technology Innovation Hub on Cyber Security created by the DST, Government of India until March 2025. In August 2025, he moved from IIT Kanpur to IIIT Hyderabad. He worked at GTE Labs as a Principal Member of Technical Staff, as Senior Staff Design Engineer at Intel Corporation, as research faculty at the University of California, Irvine, and as a Professor of Computer Engineering at Virginia Tech, Blacksburg, USA. His major research areas are cybersecurity, cyber-resilient system design, risk assessment, critical infrastructure security, and blockchain technology. Prof. Shukla had published over 300 peer-reviewed conference papers, journal articles, and book chapters, authored 12 books, and served as editor for several noted journals and technical publications.
Pranav Gokhale
Infleqtion, USA
Title: Demonstration of a Logical Architecture Uniting Motion and In-Place Entanglement: Shor's Algorithm, Constant-Depth CNOT Ladder, and Many-Hypercube Code
Abstract: Logical qubits are considered an essential component for achieving utility-scale quantum computation. Multiple recent demonstrations of logical qubits on neutral atoms have relied on coherent qubit motion into entangling zones. However, this architecture requires motion prior to every entangling gate, incurring significant cost in wall clock runtime and motion-related error accumulation. We propose and experimentally realize an alternative architecture which unites qubit motion and in-place entanglement via nearest-neighbor gates. Our approach maintains all-to-all connectivity, while minimizing qubit motion overheads. We demonstrate three key results on Infleqtion's Sqale QPU, which hosts an array of 114 neutral atom qubits. First, we perform a logical qubit realization of a pre-compiled variant of Shor's Algorithm. We find better logical-than-physical performance over a range of settings including with loss correction and leakage detection. Second, we introduce a technique for performing CNOT ladders with depth independent of both the number of logical qubits N and the code distance d. In proof-of-principle experiments with 8 and 12 logical qubits, we find ~4x reduction in error via the logical encodings. Third, we experimentally realize initialization of the [[16, 4, 4]] many-hypercube QEC code. All three results benefit from optimized compilation via Superstaq, as well as our underlying architecture uniting motion and in-place entanglement. This architecture offers a path to reducing the overhead of utility-scale quantum applications relative to architectures based on entangling zones.
Biography: Pranav Gokhale is Infleqtion's Chief Technology Officer. He was previously the co-founder and CEO of Super.tech, which was acquired by Infleqtion (ColdQuanta) in May 2022. Pranav has a PhD in quantum computer science from UChicago, where his research led to three best paper awards, over a dozen publications, and three patents. His work spans the full stack of quantum technology, from low-level pulse optimization to compilation to fault-tolerant quantum algorithm design and benchmarking. Pranav's key application focus is the intersection of quantum technology and AI.
AQ-QCAS Keynote Speakers
Greg Byrd
North Carolina State University, USA
Title: Quantum Computing for Combinatorial Optimization
Abstract: Combinatorial optimization problems arise in many real-world settings, such as logistics, supply chain management, stock portfolio optimization, and design. The challenge is to choose the best combination of choices among a set of possibilities that grows exponentially with the number of decisions. This talk will discuss the best-known quantum optimization algorithms, as well as recent advances and results.
Biography: Greg Byrd is a professor of electrical and computer engineering at NC State University, and director of the NC State Quantum Initiative. He is the Chair of the IEEE Computer Society Quantum Technical Community (QTC) and has served as general chair and program chair for the IEEE Quantum Week conference. Dr. Byrd's interests include quantum computing and high-performance parallel computer architecture.
Hari P. Paudel
Leidos Inc., USA
Title: Opportunities for Quantum Computing and Simulations for Energy Applications and Infrastructure Security
Abstract: Quantum information science (QIS) is opening new opportunities by harnessing quantum mechanics to tackle problems that are beyond the reach of classical computers. Its rapid advances are creating promising pathways to improve energy production, distribution, and consumption and minimize the security challenges. Applying quantum information science emerging technologies to real-world systems remains challenging, but Leidos is actively leveraging both experimental and computational quantum tools to strengthen the nation's energy and security competitiveness.
This presentation highlights recent advances in quantum computing and for energy applications and quantum sensing for infrastructure security. It showcases opportunities for materials chemistry and complex optimization problems in areas such as CO2 capture, energy storage, fluid dynamics, nuclear energy, and grid operations. It also reviews quantum simulations of ground-state and vibrational properties of small molecules, benchmarking current algorithms against qubit counts, basis sizes, and memory demands. The talk concludes by identifying high-value application pathways for addressing major challenges in the energy sector.
Biography: Hari Paudel is a theoretical and experimental quantum information and materials scientist in the Quantum for Energy System Technology (QuEST) and Computational Material Engineering Team at the U.S. Department of Energy's National Energy Technology Laboratory (NETL). He has more than 15 years of experience in quantum information processing and computational modeling, with expertise spanning single qubit remote coupling, ab initio and atomistic methods, and the use of machine learning and artificial intelligence for modeling, optimization, and molecular simulation. His computational background includes density functional theory (DFT) and molecular dynamics (MD), along with science driven machine learning approaches for materials property analysis and prediction.
His prior research has emphasized energy applications of 2D layered and 3D solid state materials, as well as optoelectronic devices. He has also contributed to membrane materials design for carbon capture and regeneration using microwaves. His current work focuses on materials modeling for a range of applications, including efficient energy utilization and nuclear optimization. He additionally has hands-on expertise in quantum computing and quantum simulation for small molecular systems using Qiskit and related quantum algorithm platforms. Over the course of his career, he has worked with pioneers in quantum information processing, nano optics, and nanomaterials. His research interests include quantum computing and quantum algorithm development for chemistry and materials, quantum sensing with solid state qubits, and computational design of materials for energy applications.